A built-in self-test (BIST) system of memories typically consists of a processor and a number of memories to be tested to find defects. In general during the BIST, the processor applies a set of test vectors to the memory cores. The processor then receives and evaluates the response to the test vectors to determine whether a defect exists in one or more word lines being tested in the memory. The processor may compare the results from the memory output with the predicted values to determine whether a defect exists.
FIG. 1 illustrates a processor sending built-in self-test (BIST) signals to multiple memories. The processor is configured to apply and execute a BIST to various memories, such as memory 1, memory 2, and memory 3. The memories share the built-in self-test features and algorithms of the processor. The processor couples the self-test information via a parallel bus to each memory. A large number of routing paths exist between the processor and each memory, such as twenty-five routing lines in parallel with each memory. The processor connects data lines, address lines, control lines, and march algorithm lines in parallel with each memory.
The information and routing paths pertaining to the self-test of one of the memories could be as follows. Several lines could carry test input data bits. Several lines could carry expected data bits back to the processor. Several lines in parallel to the data lines may carry the march algorithm steps. Several lines may carry the address information on which word line or word lines are to be tested. All of that information from the processor needs to be received by the memory in parallel so that the desired target memory can be vector tested to determine whether a defect exists or not in the memory cells in the memory.
The processor and memories clock cycle may be synchronized such that on each clock cycle the processor provides the necessary data and control information to test an operation on a single address or all of the addresses in a memory under test. An intelligence wrapper surrounds each memory. The processor sends all of the information needed to conduct a march sequence of built-in self-test in parallel on a particular word line to each intelligence wrapper.
This parallel architecture for sending BIST information works fine for a small number of memories that have a large byte capacity. Each memory takes up a large amount of routing paths, such as 25, from the processor. The accumulation of all of the BIST routing paths for all of the memories takes up a lot of space on a system on a chip. However, since there may be only a few large memories on a system of a chip, the cost benefit analysis is fine. However, in a system on a chip design that utilizes a large amount of small memories, such as register files, this many routing paths per memory may not be acceptable.
Another disadvantage of a parallel architecture from the processor to the memories may be that both operate in a synchronous timing cycle. The operations sent from the processor in the parallel lines occur at the clock speed of the memory. Each clock cycle, the processor sends all of the information in parallel needed to conduct a March sequence of the built-in self-test on the memory. Those operations then are executed on the memory at the speed of the memory. Those operations are also evaluated at the speed of the memory. Thus, the built-in self-test processor is generally built to run at the same clock speed as the memories during the built in self-testing. Building a built-in self-test processor that operates at a lower frequency than the memories may be significantly easier.